The present invention relates generally to the packaging and interconnection of power semiconductor devices and, more particularly, to device structures and assemblies with improved heat dissipation characteristics and low impedance interconnections.
Power semiconductor devices of various types are well known, such as power MOSFETs (metal oxide field effect transistors), and IGBTs (insulated gate bipolar transistors) which are employed in power switching applications. Prior to any packaging or interconnection, these devices generally are in the form of a semiconductor chip having an active major surface, or top side, and an opposite major surface, or bottom side. The active major surface is patterned and has metallized I/O (input/output) pads including, in the case of a power semiconductor device, at least two terminals, i.e., a device main terminal, such as the source, and a control terminal, such as a gate. In typical devices, in order to provide low impedance connections, there are multiple main terminals on the active surface, all to be connected in parallel, and one or more control terminals, likewise to be connected in parallel. The uniform opposite major surface or bottom side of the chip comprises another main terminal, such as the drain. Fabrication steps for fabricating the chip generally are performed on the active major surface, and the various semiconductor junctions internal to the chip are relatively nearer the active major surface than the opposite major surface.
Standard approaches to packaging result in the power semiconductor devices being mounted on a metal pad which is located on an insulating substrate such as Al.sub.2 O.sub.3. Such substrate provides the required electrical insulation, and additionally a good coefficient of thermal expansion match to silicon devices. The Al.sub.2 O.sub.3 insulating substrate must be as thin as possible because it is in the thermal path through which device heat is dissipated, and Al.sub.2 O.sub.3 is a relatively poor thermal conductor.
For connections to the source and gate terminals located on the active major surface or top of the chip, wire bonds are conventionally employed. Wire bond connections however have the disadvantage of resulting in relatively high source and gate inductance and resistance. In addition, in circuit topologies where multiple power semiconductor devices are connected in parallel, wire bond connections result in varying conductor lengths to the gate pads on the various devices. Such conductor length variations can cause some devices to receive gating signals before others. Because the devices thus do not all turn on or off in unison, performance degradation results.
In one typical configuration, a printed circuit board mounted above the power devices includes various control and passive elements, and leads or wires are soldered between the power devices and the printed circuit board. In another configuration, the power devices and controls are mounted on a common substrate. This configuration, however, potentially increases complexity, and pushes thermal limits.
In the context of one of the embodiments of the invention, most of the device heat is generated near the active major surface or top of the chip where the semiconductor junctions are located, rather than near the opposite major surface or bottom of the chip. Nevertheless, power semiconductor devices are typically mounted to a heat sink via the bottom of the chip, which is uniform and facilitates mounting as a practical matter. During device operation, junction temperature is the predominant limiter of device power dissipation and reliability. Power semiconductor devices are typically derated in their operating limits, that is, voltage, current, power and/or frequency are derated, based on the operating junction temperature. The higher the junction temperature, the more the operating parameters are derated and the lower the device performance.
Disclosed in commonly-assigned Fillion et al application Ser. No. 08/192,533, filed Feb. 7, 1994, entitled "Wireless Radio Frequency Power Semiconductor Devices Using High Density Interconnect", is a component package which, rather than the conventional Al.sub.2 O.sub.3 ceramic insulator below the chip, employs a direct bond copper BeO substrate which offers significantly better thermal performance. In the package described in application Ser. No. 08/192,533, a polyimide film in the range of from one to four mils in thickness is bonded over the active major surface of the power device or devices, so as to bridge to the direct bond copper surface. Vias are formed in the polyimide film over the source and gate pads, for example, employing laser ablation, plasma etch or wet chemistry. The entire polyimide film surface is metallized and patterned, connecting the source and gate pads to the direct bond copper metal, and/or to the source and gate terminals of other chips. The structure described in application Ser. No. 08/192,533 has improved thermal, mechanical and electrical performance compared to prior art configurations. Nevertheless, further improvements can be made, particularly in the context of heat dissipation. Additionally, the structure described in application Ser. No. 08/192,533 is not suitable for the stacked device configuration disclosed herein for half bridge circuit topologies.
Thus, a common circuit topology, particularly relevant in the context of the present invention, is the half bridge in which two semiconductor power switching devices, such as power transistors, are connected in series. Employing MOSFET terminology for example, the source terminal of one device is connected to the drain terminal of another device, and the two devices have respective, independently connected, gate control terminals. Employing bipolar terminology as another example, the emitter terminal of one device is connected to the collector terminal of another device, and the two devices have respective, independently connected, base or gate control terminals. Other conventional circuit elements include series gate resistors, bidirectional Zener diodes for gate protection, and output protection networks comprising capacitors and diodes. Other circuit topologies relevant in the context of the invention include multiple half bridge circuit topologies wherein several half bridge integrated circuit chip sets are connected in parallel for increased power-handling capability.
While implementation of the aforementioned half bridge circuits may seem straightforward, there are practice difficulties in realizing these circuits with actual devices. Typical assembly methods implementing the aforementioned half bridge circuit topologies place the semiconductor devices in a common plane, with wire bonds to the source and gate leads as described hereinabove. Series resistance losses and gate parasitics can result, particularly at higher switching speeds. With multiple half bridge integrated circuit chip sets, gate parasitics and series losses are even more severe.
In order for the individual devices to turn on and off at the same time, it is desirable for the conductor lengths to the various devices, most particularly the gate conductors, to all be of the same length. In addition, low-impedance connections are highly desirable.